In the design and manufacture of semiconductor structures, particularly those containing both integrated control circuits and power devices, it is frequently desired to electrically isolate different device regions placed within the same semiconductor body. The need for such isolation is especially strong when control circuitry and power devices are used in the same semiconductor wafer or die. Control circuits are generally arranged to have all their device contacts on the top surface of the wafer or die where they may be readily interconnected. Power devices, on the other hand, often must utilize the entire thickness of the semiconductor die. This is especially true when very high voltage or very high current power devices are needed, when there must be a very high degree of isolation between the power devices and the control circuitry, or when large amounts of power must be handled. In this situation, one of the terminals of the power device must appear on the back or bottom surface of the semiconductor die. Such devices are referred to as bottom-contact devices. As used herein, the words "bottom-contact" are intended to refer to devices or device regions having at least one contact on the rear or bottom face of the die or wafer. Bottom-contact devices will generally also have other contacts on the front or top face of the die or wafer. As used herein, the words "top" or "front face" of the die or wafer are intended to refer to the surface where contacts to the control circuitry are generally placed. As used herein, the words "control circuits" or "control circuitry" are intended to refer to all manner of digital or linear devices, or combinations of devices, which may be used in conjunction with power devices, and which are integrated within the same semiconductor die as the power device.
Prior art semiconductor device structures and methods have not provided convenient means for obtaining bottom-contact power devices and top-contact control circuitry in the same semiconductor die, with electrical isolation therebetween. With the prior art, it has generally been necessary to use multiple masking steps involving etched grooves, buried layers, and/or deep side wall diffusions to create the isolation regions surrounding the areas in which the devices or circuits are to be constructed. These techniques are undesirably expensive and may limit the attainable device performance.
A further problem with prior art structures and methods is that the doping type, density, and gradient of the semiconductor regions used for constructing the power devices and those used for constructing the integrated control circuitry usually cannot be varied independently, or can only be varied with great difficulty or within narrow limits. For these reasons, prior art means and methods have limited the ability to independently optimize both the power devices and the integrated control circuitry in the same wafer or die.
Accordingly, it is an object of this invention to provide an improved process for epitaxially fabricating electrically isolated device regions.
It is another object of this invention to provide a process for fabricating electrically isolated device regions requiring only a single epitaxial growth operation.
It is a still further object of this invention to provide an improved process for fabricating epitaxially isolated structures having regions for top contact circuitry and regions for bottom contact devices.
It is yet another object of this invention to provide an improved process for fabricating isolated device regions of different resistivites in a single epitaxial growth operation.